[rockyjohn]

My tweaking has not been as productive I had hoped.
I have not touched the primary timing settings - 4-4-4-12, nor these:

CPU Host Clock Control
CPU Host Frequency (Mhz)------------333
PCI Express Frequency (Mhz)----------100
Performance Enhance-----------------Standard
System Memory Multiplier (SPD)-------2.4

DDR2 OverVoltage Control -----------+0.3
FSB OverVoltage Control -------------+0.1
(G)MCH OverVoltage Control ---------+0.1

Day one went well - slowly changing from stable to day one - as noted below with default (unstable) for reference. At end of day one I ran Memtest overnight for overnight for 9 passes without errors.

I made several successful adjustments on morning two - also shown below - then the I started losing ground.


-----------------------------Default---Stable----Day1-----Mid2
ACT to ACT Delay (tRRD)--------3--------4--------4--------4
Rank Write to READ Delay-------3--------11-------6--------5
Write to Precharge Delay--------6--------5--------5--------5
Refresh to ACT Delay----------52--------62-------58------58
Read to Precharge Delay--------3--------6--------6--------4
Static tRead Value-------------6--------10--------8--------8

I lowered Rank Write to READ Delay to 4 and had Memtest error.
I returned it to 5 and test error - even though this had passed a 3 pass test before.
Raised to 6 and retested - failed again.
Not wanting to push this higher than the overnight pass configuration, I left it at 6 and and raised Read to Precharge Delay back to 5 and it passed. Lowered Static tRead Value to 7 and it failed. Raised it back to 8 - where it had passed one trial before - and it failed. Left it at 8 and lowered Read to Precharge Delay to 4 to make all settings match previous good configuration and it failed. Now I am going to raise it back to 6 to match the configuration I ran last night and run it tonight - and hope I have not lost any ground. The failed tests are summarized below, starting with the good mid-day and showing changes.


____________________________-------------CHANGES--------------_____
--------------------------Mid2---Fail--Fail--Fail-Pass--Fail--Fail--Fail--Final
ACT to ACT Delay (tRRD)----4------------------------------------------4
Rank Write to READ Delay----5-----4----5----6-------------------------6
Write to Precharge Delay----5------------------------------------------5
Refresh to ACT Delay-------58-----------------------------------------58
Read to Precharge Delay---- 4--------------------5----------------4----4
Static tRead Value----------8--------------------------7----8----------8

Any suggestion on a better course for trying to reduce the settings?

Rocky
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