[stasio]

Originally Posted by killersjp

Look forward to the new ud5 bios, but can someone explain the features of channel interleaving and rank interleaving. Thanks

Info from XS:

Channel Interleave: Higher values divide memory blocks and spread contiguous portions of data across interleaved channels, thereby increasing potential read bandwidth as requests for data can be made to all interleaved channels in an overlapped manner. For benchmarking purposes when using three memory modules, a 4-way interleave may surpass the scoring performance of setting 6-way interleave depending on the benchmark and operating system used (32-bit vs. 64-bit). We did find however that a 6-way interleave was capable of a higher overall BCLK for Super PI 32M than using a 4-way interleave setting (unless of course you run single- or dual-channel and appropriate channel interleaving thus decreasing load upon the memory controller).

Rank Interleave: Interleaves physical ranks of memory so that a rank can be accessed while another is being refreshed. Performance gains again depend on the benchmark in question. For 24/7 systems using triple-channel memory configurations there is no advantage to setting this value below 4 while Channel Interleave should be left at 6 for best overall system performance.