Memory Timings Explained W/ Suggested Timings & Memset VS. BIOS

[Joesoft]

Hi everyone and thanks to artdrivers and Lsdmeasap for the answers.
Here I attach two captures of my complete System Voltage Control of my bios

As you see, I have increased the DDR OverVoltage Control to +0.1 and set the ATC Relay to 64 (before it was 48 I think so)

artdrivers, you suggest me to increase the value of FSB OverVoltage Control. I am going to test it but Im still waiting for complete a download in emule.

Lsdmeasap, thanks to this forum I found the way to switch my bios menu to an advance menu. I was going crazy because the only way to see advance options was with the easyturner6.

Again thanks, and Im going to make changes in FSB OverVoltage as soon as emule completes the download

Best regards

[Joesoft]

Here is the second snapshot of my bios.
See you soon

[Lsdmeasap]

OK, ya what you are calling ATC Delay is refresh to act delay, and for 4GB you need to set that to at least 52-62 for now until you get a bit more stable then you can try lower

[Joesoft]

Hi again.
As I told you, I was waiting for completing a download in emule before test my pc with the values you suggested me to try to fix my problem.
My pc was working ok for two days. Yesterday at night, I viewed my emule and in few minutes it will finish.
Today, earlier, my pc was in another session. It rebooted
Then I reseted it, entered my session, run my messenger, emule, and... a blue screen!
Again I reseted my pc, entered my bios and increased the FSB OverVoltage Control in 0.1+ like you suggested me. All seems ok.
I didn't touch the DDR OverVoltageControl. It mantains the 0.1+ (1.9v)
Im still doing tests.
I will keep in touch.

Best regards

Joe

[Lsdmeasap]

So all still Good? Hope so, if not please give us your settings again that fail and we will advise

[MarktheC]

Hi Lsdmeasap,

Thanks for all the wonderful info here: When I recently bought a new PC, it helped me immensely in understanding all about the RAM technology I now had. I googled and researched a lot, and there are a couple of things that might be of interest (or at least my noobishness might entertain!)

1) You write:

tRAS = tCL + tRCD + tRP (+/- 1) so that it gives everything enough time before closing the bank.

... Everybody else says that also, but I don't think that's right!

A DDR2 spec says:

Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).

... a diagram in that PDF shows "RAS Cycle Time = Bank Active time + Bank Precharge time": i.e. Bank Active is followed by Precharge.
(It also shows: "RAS Cycle Time >= tRC, Bank Active >= tRAS, Bank Precharge time >= tRP".)

If Bank Active time preceeds and does not include Precharge, how can tRAS = tCL + tRCD + tRP (+/- 1)?

I suspect actually that, tRAS = tCL + tRCD + tXXX, where tXXX is some unspecified internal chip operation minimum time, and that tXXX just happens to be have the same numerical value as tRP (+/- 1), in the same way that tCL, tRCD & tRP just happen to often have the same numerical value.

2) Isn't tRD a little mysterious?

I googled high and wide and even download a few Intel MCH spec docs, and tRD is not documented for recent DDR2 MCH chips!
It is surely an MCH configuration value, but not documented. I did find a forum post by the author of the memset program where he and others were discussing which MCH register it was in.

As near as I can tell, tRD is more or less the equivalent to tCL, but on the CPU/MCH side of the bus, rather than on the MCH/Memory side of the bus.
(tCL is the clock delay - memory clock - between the MCH giving a read command (CAS) to the memory and data becoming available, whereas tRD is the clock delay - CPU FSB clock - between the CPU giving a read command to the MCH and data becoming available.)

Given that tCL is just about the most important memory parameter, and the one of the first things that people tweak, it's surprising that many 'how to tweak memory speed' articles don't even mention tRD.
The AnandTech: ASUS ROG Rampage Formula: Why we were wrong about the Intel X48 link on the first page of this thread is about the only place I found that talked about it in depth. They have a formula which can more-or-less be arranged into:

tRD > (tCL + x) * FSB / DRAM_Freq

...where 'x' is a funny parameter not explained well.

I'd like to think x is tCCD (usually =2?), because that would make sense given the process. Or perhaps the formula is:

tRD > (tCL / DRAM_Freq + x) * FSB

... where x = 5/1000 (5ns, plucked out of the air...)

[Lsdmeasap]

Well tRAS is a "Usually" type of thing, sometimes it can differ. You can see the same noted here by the maker of Memset
Tweakers.fr

tRD, ya it can be mysterious at times, it's new tech so ya never know what to expect.

From the above linked site

-Performance Level / Read Delay (tRD).
tRD is the number of memory clocks from DRAM Chip Select# assert
to Host Data Ready# assertion on the FSB.
Hight influence on performance and stability.

[inforcer]

hi all, i got a problem setting the patriot 2x2gb ddr3 llk kit, it's not working in dual channel mode on my ma790xt-ud4p. i already post the details here :
Ga-ma790xt-ud4p + pdc34g1333llk
pls help

[artdrivers]

inforcer can you try another cpu? That 955BE has the dual channel memory controller on it. You may have a defective memory controller.
AMD Phenom II X4 955 Black Edition Processor Introduction :: TweakTown

[artdrivers]

inforcer there is a later bios to flash to scroll down on this url.---->
GIGABYTE - Support&Download - Motherboard - BIOS - GA-MA790XT-UD4P (rev. 1.0)