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Rumoured AMD K9 processor specs.
It seems, K9 will have an integrated DDRII controller
Processor will feature speculative branching (up to 8 branches), and probably some rollback cache in case a branch is predicted wrong...
Processor will probably have 3 (!) fully-fledged ő87 blocks, 3 SSE2 and 2 ALU blocks. Decoders will be capable of organizing them by three (FPU + SSE2 + ALU) for maximum performance.
K9 will possibly utilize AMD’s old patent, describing integrated Peltier element packaging
Processor might have several buffers, a kind of L0 cache. For example, a 4Kb buffer will precede and follow FPU for making its operation (SSE2, 3DNow) continuous.
Ę9 might also support L3 cache for commented code. I.e. decoder will be capable of acting right in L3 inserting comments into special fields.
Pipeline will probably feature 15 ALU stages, 20 FPU stages.
I-cache and decoder will perform at double speed.
AMD might situate L3 cache on crystal using 1T-SRAM.
Hyper Transport II – expected to be something like Octal Data Rate (Yellowstone) with about 1GHz carrier clock. As a result throughput will reach 25Gb/s in 16x16 configuration.
Interprocessor protocol (MOESI) will be updated and improved.
The very fast bus will provide a very interesting feature of sharing free executive units between two processors. I.e. if the first has FPU loaded and the second has it free, then the latter can handle requests from the decoder of the former.
05-05-2003, 07:02 AM
If AMD has a good built in peltier...i would switch to AMD b/c a good TEC can get 10C and think of the o/cing ability, unless they make it so you cant unlock the multiplier
AMD is advertising this position for a K9 bus and Northbridge engineer.
DESCRIPTION OF POSITION: Verification of K9 microprocesor with emphasis on the K9 external bus and Northbridge. SPECIFIC JOB FUNCTIONS: 1. Works with Applications Engineering to develop functional specifications for new products.2. Reviews methods appropriate to develop new products and selects best method of achieving desired performance and function goals.3. Utilizes technical skills in multiple product developments.4. Works on related projects and/or assignments as needed.5. Use Knowledge of verilog, C++, Perl and computer/microprocessor architecture and design to verify the external interfaces of the cpu and the interal logic structures that drive these interfaces. PREFERRED EDUCATION AND EXPERIENCE: BS with 7+ years exp or MS degree with 5+ years in Electrical or Computer Engineering. Should have expertise in Bus architecture and verification for microprocessors and computer systems.
AMD K9 to come in 2005 or 2006?
Just a couple of days ago a reader very close to Austin, Texas laboratory told me that the code-named K9 CPU has been in development for just about six month. The project K9 hit the drawing board, but no silicon has been touched at all, he added. Despite of these facts, a Japanese web-site PC Watch issued some preliminary information about the next-generation CPUs from AMD.
Historically it took three to five years to develop architecture, design actual microprocessor and ramp up the production of a CPU. As a result of more efficient execution and solid experience, both Intel and AMD were able to shorten this period to about two to three years. Unfortunately, despite of the fact that AMD’s K8 was almost ready to go in 2001, the actual chips come out only this year due to problems with their fabrication process; so, there is a four years gap between the K7 and K8.
Sources claim that actual details of the K9 architecture will be announced in a year, sometime in Fall 2004, whereas, in case everything goes well, the AMD K9 microprocessors will emerge in 2005 or 2006. Nevertheless, we may discuss some compulsory and very probable facts about the K9 processors even now.
First of all, let us touch upon the CPU FSB. The Hyper-Transport is about to prove its efficiency and cost-effectiveness as an interconnection mechanism between the microprocessor and other components of the system. We may presume that the K9 processors will inherit Hyper-Transport technology from the K8. There will be a major gap between K9’s and K8’s FSBs, hence, AMD’s next-generation CPUs are very likely to utilize improved version of the Hyper-Transport bus.
Secondly, since the 64-bit software will not have the largest market share neither by 2005 nor 2006, AMD K9 will also utilize the x86-64 (currently renamed to AMD64) architecture.
Finally, all hardware developers and makers will support, or will have to support, Microsoft’s Next-Generation Secure Computing Base code-named Palladium. The upcoming Intel Prescott microprocessor will support the La Grande technology, whereas AMD’s K9 will boast with something similar.
Considering the currently discussed timeframe I believe that the AMD K9 processors will be fabricated using 65nm manufacturing process. Their core-speeds will surely be higher compared to what AMD has now, but there is no point to guess about that as we still know practically nothing about the architecture of AMD’s next-generations K9 CPUs.
AMD sets date for son of Opteron
Advanced Micro Devices, which released its Opteron chip only six months ago, is already planning to come out with a successor in 2005.
The Sunnyvale, Calif.-based company is "working like crazy" on the K9, an underlying architecture, or blueprint, for a new generation of chips, said Fred Weber, chief technology officer of AMD's computational products group, during an interview at the Microprocessor Forum here Wednesday.
Chips based on the K9 architecture will likely be released--at least in sample quantities--by the second half of 2005, Weber said. AMD engineer Randy Allen is overseeing the project.
Chip companies release new architectures every three to four years, but the process is becoming increasingly difficult because of power consumption and the shrinking size of transistors. The K8 architecture, the basis for the Opteron released in 2003, was unveiled in 1999 by Weber at the same conference. Chips based on the K8 design were originally due at the end of 2001.
Although Weber declined to provide technical details about the K9, processors that are based on the architecture will likely be capable of containing multiple chip cores--the "brain" of the chip--and of running one or more application threads. Putting more than one core inside the processor boosts performance in a relatively efficient way, Weber and others at the conference said. Opteron, in fact, is designed in a way that enables a second core to be added, Weber noted.
"We will have a multicore product," Weber said.
AMD is also looking at adding threading to future chips. Simultaneous multithreading essentially enables a chip to run two applications, or two "threads" of the same application, at the same time--thereby reducing the time it requires to complete a task. Threading, however, does not provide as much of an improvement to overall performance as multicore technology does, according to Weber.
Most chips that come out over the next few years will likely feature a host of new materials and structures, such as multiple-gate transistors and strained silicon layers, according to analysts.
More information (http://news.com.com/2100-1006-5091845.html)
10-17-2003, 12:38 AM
:drool: reading the description in the first post nearly made me wet myself :cackle:
however, this quote:
Finally, all hardware developers and makers will support, or will have to support, Microsoft’s Next-Generation Secure Computing Base code-named Palladium.has me concerned. Although, i must admit I don't know much about it. I should probably do some reading first...
<center>AMD talks about future CPU micro-architecture innovations
AMD K8, AMD K9, AMD K10, AMD K11?</center>
Besides some facts about AMD’s next-generation project code-named K9, the company’s CTO Fred Weber also disclosed a number of details concerning forthcoming CPU micro-architectural innovations at his keynote at Microprocessor Forum 2003.
In general, the key peculiarities of future microprocessors reflect not only AMD’s vision of further CPU development, but also contain a number of approaches other chip companies plan to deploy. It is very interesting to note that these innovations are agnostic to CPU instruction set; e.g. such measures of performance boosting will be engaged by virtually all microprocessor families, such as x86, PowerPC, EPIC, ARM, SPARC and so on.
According to AMD’s Fred Weber, the paramount forces to be deployed by the next-generation chips, such as AMD K9, AMD K10, etc are as follows
Chip level multiprocessing
Huge scale MP machines
Much higher performance superscalar, out of order CPU core
Media/vector processing extensions
Branch and memory hints
GHz performance IO
Security and virtualization
Static and dynamic power management
In fact, there is nothing really new in those patterns and some of them are either already available, or are just around the corner.
For instance, we do already have multi-threaded architectures, such as Intel’s Hyper-Threading, in the market, we are probably going to see more innovations in this field from Sun, IBM and AMD. I would even expect some multi-threading to emerge in the K9 design, but since the chip is quite far from here, we cannot state anything for sure.
Chip level multiprocessing is planned to be available in high-end IBM’s Power5 processors next year, while Sun, Intel and AMD plan to debut with their dual-core chips in 2005. In respect of AMD, its first dual-core chips will be based on K8 architecture, according to the company. Intel will also introduce dual-core Xeon and Itanium processors in future.
Operation at unbelievable frequencies, huge caches as well as powerful CPU and I/O buses are inevitable parts of performance progress. There are no doubts that AMD K9, AMD K10, AMD K11 in addition to other microprocessors will work at high core-speeds and employ large L1, L2 and possibly L3 caches. Obviously, the K9 will hardly achieve 10GHz, but K10 will surely hit this important milestone. It will be amazing in case after 10GHz we will see 20GHz, 30GHz and so on, just like we witnessed the thorny way from 10MHz to 33MHz in the eighties.
Other innovations, such as media and vector processing extensions, branch and memory hints and so on, are also found in the majority of today’s CPUs starting from Pentium Pro, Pentium MMX and AMD K6-2 3DNow!. Expect more extensions of such kind in AMD’s Athlon 64 processors as well as K9 and K10 chips.
We already know from our previous reports that AMD K9 will support Palladium security capabilities from Microsoft, the presentation probably confirms this previous statement.
Finally, it is very interesting to hear about dynamic power management in desktop processors. So far there have been only static kinds of power management, while dynamic was a prerogative of mobile processors. Looks like we are going to have the feature enabled in desktop CPUs as well.
To sum up, the way from 5MHz to 3200MHz was exciting and took 25 years. Will there be a complicated way from 3.20GHz to 2048GHz in Intel’s and AMD’s projects during the next two and a half decades implementing the principles claimed by AMD and Intel executives nowadays?
Although the chip was not disclosed on the roadmap, the next-generation K9 will ship very late in 2005, Meyer said. Analyst Krewell added there is a strong possibility that the die will contain more than one processing core.
<center>AMD K9s scheduled for late 2005, 2006
Low power chips will be the name of the game</center>
ROADMAPS SEEN by the INQ reveal plans for AMD K9 Opterons to arrive in the first half of 2006, and gradually during that year to shove out the K8s into obscurity.
The K9 processors will be introduced as the 870, 868 and 866 Opterons – with these chips being released during the first half of that year.
In the second half of the year, the K9s will migrate to the top end 874 and 872 series, while the earlier introductions will shuffle their way down the Opteron line.
And further details have emerged of low power AMD chips for both the server and the mobile market – with 55 watt and 30 watt processors in AMD’s lineup, as it moves to migrate to the 90 nanometer process. These will attack Intel in the blade and rack dense server market.
There will be 846s, and 246s running at 55 watts as early as the first quarter of 2004. When K9s come using smaller processes, AMD hopes to achieve even lower wattages on the future chips.
By the end of next year, there will be 840s and 240s at 30 watts, according to the roadmaps we’ve seen.
AMD will cut prices on its standard wattage Opterons as it introduces the new lower power versions – all indications are by a serious amount. That means a furious and fast price war between it and Intel on the server front for the whole of 2004.
11-13-2003, 10:29 PM
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