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Thread: Intel Tejas

  1. #11
    Join Date
    Aug 2003


    I am gonna call bs on the 4000mhz FSB speed. There is no way we will have memory that runs that fast to keep up with it. There are other limitations as well.

    FX5900 - 3DMark2001 [20,566] - 3DMark2003 [7,281] - Aquamark3 [56,694]
    Ti4400 - 3DMark2001 [16,028]

  2. #12
    Join Date
    Jul 2002


    <center>Intel CPU Roadmap Changed: Tejas Postponed to 2005
    Prescott to Dissipate 120W?

    Intel postponed the release of its highly acclaimed Prescott processor from Q2 to Q4 2003, but, as we know already, the 90nm chip isn't expected to be available in quantity until late Q1 2004 or possibly even later. This delay has also affected the release of the future-generation Tejas processor.

    Both the Prescott and Tejas processors are based on Intel’s NetBurst architecture already utilised in its Pentium 4 processors. Prescott and Tejas are both expected to include NetBurst enhancements which will influence CPU performance the most. First of all, the L1 cache will be enlarged from 8KB (Northwood) to 16KB for the Prescott and 24KB for the Tejas. Secondly, Tejas and Prescott will include 16K uOps Trace Cache, a substantial improvement over Northwood’s 12K uOps. Thirdly, the L2 caches of Tejas and Prescott chips made using 90nm technology will be 1MB, while the 65nm Tejas is projected to have 2MBs of L2. Additionally, in an attempt to lower the impact of deep-20+ stage pipeline on actual performance, Intel will implement a new, more efficient branch prediction mechanism in its forthcoming microprocessors. Finally, Intel will raise both core and FSB clocks, resulting in even faster computing speed for its next-generation NetBurst processors. Furthermore, following Intel’s recent general policy, presuppose enhanced efficiency of the Hyper-Threading technology as well as several new instructions (Prescott New Instructions, Tejas New Instructions) to optimise certain operations with every new generation of NetBurst chips.

    As you can see from the previous paragraph, Prescott and Tejas processors are extremely impressive on a number of points – they become faster in terms of clock-speed and they become more efficient from an architectural point of view. Unfortunately, as they become faster, they consume more power than their predecessors; as NetBurst architecture bottlenecks are considerably enhanced, the transistor count increases, and, in the end, it's trickier to manufacture such a chip.

    We witnessed earlier this year how Intel had to start to augment the Vcore of its 90nm Prescott microprocessors making them incompatible with already existing infrastructure. At this point we see that this was only the beginning – the company has to rework its Socket T CPU and platform specifications for the same purpose. PCW reveals (see attachment) that Prescott processors in LGA775 form-factor could typically consume up to an incredible 120W!

    High CPU power consumption could lead to a lot of different and unwanted effects within the microprocessors. We already know what the electromigration effect is, based on the Northwood example, later we may face the same on other microprocessors as well. Regrettably, this is a vicious circle for Intel; it needs to pump up the core voltage to pump up the clock-speed, but, at the same time, keep power consumption [and heat dissipation] at an acceptable level; otherwise, it will have to enhance the thickness of dielectric under the transistor gate and channel to avoid dielectric breakdown or tunnel effect – a measure that is used by some other CPU makers and that holds the core-frequencies from increasing further at some point. Certainly, there is a way for Intel to solve these issues, but it takes time and the company may have to reschedule the implementation of some of its projects.

    Based on the points mentioned herein and information received from unofficial sources, I believe that Intel will launch the Tejas processor in early 2005 (mass-quantities), and not late 2004, as previously reported.

    xbit / PCW / edited Japanese translation

  3. #13
    Join Date
    Jul 2002


    Intel Tejas & socket 775 unveiled

    <img src="">

    While the majority of the AnandTech staff were hard at work in Las Vegas covering CES, a quiet staff member was touring the streets of Taipei.

    During his visit to Taipei he came across some information shared by some very good contacts about Intel's Prescott successor - Tejas. Very few people caught on to the fact that we actually talked about Tejas on AnandTech years ago as we heard about the codename before Prescott and even before Northwood, hidden in an Intel presentation that hadn't properly been cleaned up. Originally Tejas was listed as the first Intel CPU to have a 1.2GHz FSB, but now we know a bit more about the CPU.

    Apparently a total of 10 Tejas samples have been shipped out to various friends of Intel, all running at 2.8GHz. What's also interesting to note is that our sources have informed us that at 2.8GHz Tejas uses around 150W of power - about 50% more than Prescott at the same clock speed.

    Given that Tejas is still a 90nm part, it would be unlikely that the additional power consumption would be due to a larger cache as that would make the die huge and isn't Intel's style to increase cache size without shrinking the die further. If the power figures we've been given are indeed correct, one possible explanation would be that Tejas is indeed some variation of a multicore CPU. While it is unlikely that Tejas includes two discreet Prescott cores on die, there is a chance that the two cores (if they exist) could be sharing data caches and maybe other units. A multicore Tejas would explain the jump in power consumption, and it is in line with Intel's strategy although it does seem sooner than expected.

    The 10 Tejas samples are all LGA-775 CPUs and luckily our contact was able to gather some pictures of the CPU and the interface so you all can get a glimpse of what is soon to come. We had to blur out some parts of the pictures to protect the identity of our sources, but you'll still be able to see what's important.

    More information


  4. #14
    Join Date
    Jul 2002


    Intel Tejas pushed into Q2 2005
    Prescott follower delayed once again...

    After numerous delays faced by Intel’s Pentium 4 “Prescott” and “Dothan” processors, it is not really big news that Intel is pushing code-named Tejas processor into the second quarter of 2005, about half a year later than according to the original schedule.

    Intel’s code-named Tejas microprocessor, the fourth-generation NetBurst CPUs, will have core-speeds at around 4.0GHz – 4.20GHz, probably a faster Quad Pumped Bus, tangibly enlarged caches (24KB L1 cache, 16K uOps Trace Cache, 1MB L2 cache [probably 2MB for 65nm version]), a more efficient branch prediction mechanism, a new set of instructions known as “Tejas New Instructions” as well as improved Hyper-Threading organization. In addition, the Tejas may enable long-awaited 64-bit enhancements to x86 architecture or may increase the number of executive units.

    Instead of Tejas, Intel will kick-off 4.20GHz Pentium 4 Prescott chip in Q1 2005, the source indicated.

    First Tejas processors will be made using 90nm fabrication technology, while CPUs due out later will be manufactured at 65nm nodes. Nevertheless, there are rumours that Intel will use “another”, improved, version of its Strained Silicon technology to produce Tejas chips in early 2005. According to what was told by analysts familiar with the matter, Intel will change dielectric it uses in transistors with its next-generation process.

    Provided that the information about revamped manufacturing technology for Tejas processors is correct, its delay may mean that Intel is concentrated on making the best technology possible to provide excellent frequency headroom amid reasonable power consumption by upcoming chips. On the other hand, delay of Tejas means Intel is pretty confident in Prescott and expects its first desktop 90nm part to be powerful enough for securing Intel’s position until Q2 2005.


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